Traditional planar metal oxide semiconductor (MOS) transistor technology is approaching fundamental physical limits for certain transistor features past which it will be necessary to employ alternate materials, processing techniques, and/or transistor structure to support continued transistor performance improvement according to Moore's Law.
One such paradigm shift is a non-planar MOS structure. One particular non-planar MOS structure is a non-planar tri-gate transistor. A tri-gate transistor employs a three-dimensional gate structure that permits electrical signals to conduct along the top of the transistor gate and along both vertical sidewalls of the gate. The conduction along three sides of the gates enables, among other improvements, higher drive currents, faster switching speeds, and shorter gate lengths, simultaneously increasing the performance of the transistor while occupying less substrate area versus a planar MOS structure. The tri-gate structure further decreases the amount of current leakage, a problem to which ever shrinking planar MOS devices are prone, by improving the short channel characteristics of the transistor.
Another paradigm shift involves using strained semiconductor material for various portions of a transistor. Adding tensile or compressive strain to a semiconductor (depending on the particular application) lattice increases the carrier mobility within the strained semiconductor. In particular, for an NMOS device imparting tensile strain to a semiconductor increases the electron mobility (i.e., dominant charge carrier in an NMOS device). The increased carrier mobility in turn allows for higher drive current and corresponding faster switching speeds.